
Notes on caches
---------------

 The caches are not currently finished, not connected to the rest of
 the memory subsystem, and in fact not currently compiled. I'm not sure
 whether to continue working on them or not; probably I will eventually,
 but this is a lower priority.

 CP0 implements two Diagnostic Status bits in the Status register called
 IsC and SwC; they can be used by the OS to determine the cache geometry
 exactly, for example. These can be tested by the appropriate accessor
 functions in cpzero.cc.

 Cache isolation (IsC = 1) means the cache is never refilled and all
 accesses are considered hits; stores write into the cache and do not
 write into memory.

 Cache swapping (SwC = 1) means the instruction cache and data cache
 are switched, so that instruction fetches go through the data cache
 and load/store instructions go through the instruction cache.

