
Exception prioritizing
----------------------

 It is possible for more than one exception to occur during the emulation
 of the same instruction.  The MIPS architecture has a system for
 determining which of a set of conflicting exceptions is reported to
 the exception handler.

 When two or more exceptions occur on the same execution of the same
 instruction, only one is reported, according to the following priority
 list. The ordering is by exception code (EXCCODE) and mode of memory
 access (MODE), where applicable. Each ordered pair (EXCCODE, MODE)
 below has the priority listed in brackets. * denotes a position where
 any value matches.

    [1] Address error - instruction fetch 
        (AdEL, INSTFETCH)

	[2] TLB refill - instruction fetch
		TLB invalid - instruction fetch 
		(TLBL, INSTFETCH)
		(TLBS, INSTFETCH)

	[3] Bus error - instruction fetch
		(IBE, *)

	[4] Integer overflow, Trap, System call, Breakpoint, Reserved
		Instruction, or Coprocessor Unusable
		(Ov, *)
		(Tr, *)
		(Sys, *)
		(Bp, *)
		(RI, *)
		(CpU, *)

	[5] Address error - data load or data store
		(AdEL, DATALOAD)
		(AdES, *)

	[6] TLB refill - data load or data store
		TLB invalid - data load or data store
		(TLBL, DATALOAD)
		(TLBS, DATALOAD)
		(TLBL, DATASTORE)
		(TLBS, DATASTORE)

	[7] TLB modified - data store
		(Mod, *)

	[8] Bus error - data load or data store
		(DBE, *)

	[9] Interrupt
		(Int, *)

